The present invention relates generally to a semiconductor integrated circuit and operating method and more particularly a semiconductor device having a memory and logic circuit integrated in which a burn-in test may be simultaneously executed.
As the operating speed of a microprocessor unit (MPU) increases, the system memory is also required to increase its operating speed. The system memory typically includes a dynamic random access memory (DRAM). If the operating speed of DRAM fails to increase along with the operating speed of the logic included in the MPU, the processing performance becomes limited by the operating speed of the DRAM. To solve this problem, a semiconductor integrated circuit has been developed in which a DRAM and logic are both integrally placed on the same semiconductor chip.
In a semiconductor device, a burn-in test is commonly performed after manufacturing in order to screen and eliminate initial latent defects (infant mortality). A burn-in test subjects the semiconductor device to stress by applying high temperature (e.g., 125xc2x0 C.) and a power supply voltage above the rated voltage indicated by the specification in which the device is guaranteed to reliably operate.
It is desired, in semiconductor integrated circuit having DRAM and logic, to simultaneously apply stress to both the DRAM and logic circuits during the burn-in test, thus, reducing test time and decreasing costs.
Japanese Laid-Open Patent Publication No. Hei 11-134900 discloses a semiconductor integrated circuit capable of applying a burn-in test to both a memory and a logic circuit. Such a semiconductor integrated circuit is illustrated in FIG. 1.
Referring now to FIG. 1, a block schematic diagram of a conventional semiconductor integrated circuit is set forth and given the general reference character 101.
Conventional semiconductor integrated circuit 101 includes a DRAM 102 and a logic circuit 103.
Logic circuit 103 includes multiplexers (108 to 111). In the burn-in operation, a signal is externally input into logic circuit 103. Logic circuit 103 is operable in response to an external input signal during burn-in.
Conventional semiconductor integrated circuit 101 also includes a vector generator circuit 112 and a refresh counter and control circuit 106. During burn-in operation, DRAM 102 can receive addresses, instructions, and data necessary for the burn-in operation from vector generator circuit 112 and refresh counter and control circuit 106. In this way, DRAM 102 and logic circuit 103 can be made to operate independently and simultaneously, so that a burn-in time can be reduced.
Conventional semiconductor integrated circuit 101 also includes a multipexer 113. Through multipexer 113, vector generator 112 receives vector generation control signal MBICMD, write data initial values (DIN0 to DINn), data inversion control signal DININV, read signal LDRD, and write signal LDWT. Write data initial values (DIN0 to DINn) are signals that set the initial values of the write data. Data inversion control signal DININV, read signal LDRD, and write signal LDWT are signals for inputting a read/write command into vector generator circuit 112. Vector generator circuit 112 also receives a carry signal RCRY generated by refresh counter and control circuit 106.
Vector generator circuit 112 includes a column address generator circuit 114, a segment address generator circuit 115, a write data generator circuit 116, a function command generator circuit 117, and an address generation control circuit 118.
Column address generator circuit 114 generates column address signals (CA0 to CAn). Segment address generator circuit 115 generates segment address signals (S0 to Sn). Write data generator circuit 116 generates write data signals (D0 to Dn) based upon write data initial values (DIN0 to DINn) and write signal LDWT. Function command generator circuit 117 generates read signal RD and write signal WT.
DRAM 102 receives column address signals (CA0 to CAn), write data signal (D0 to Dn), read signal RD, write signal WT, vector generation initiation signal MBI, and segment address signals (S0 to Sn) from vector generator circuit 112.
An input circuit 104 is provided on an input side of DRAM 102. An output circuit 105 is provided on an output side of DRAM 102. DRAM 102 also includes refresh counter and control circuit 106 and segment address decoder 107. Refresh counter and control circuit 106 generates a refresh signal and includes an address counter for generating a row address for selecting a row or word line to refresh.
Segment address decoder 107 selects one segment among four memory segments (not shown) provided on DRAM 102 based on segment address signals (S0 to Sn).
Conventional semiconductor integrated circuit 101 further includes logic circuit 103. As previously mentioned, logic circuit 103 includes multiplexers (108 to 111). Multiplexers (108 and 109) are provided on an input side front stage of input circuit 104 of DRAM 102. Multiplexers (108 and 109) each receive an input signal from input terminals (IN1 to INn), respectively and another signal from within logic circuit 103. Multiplexers (110 and 111) are provided on an output side next stage of output circuit 105 of DRAM 102. Multiplexers (110 and 111) each receive an output signal from DRAM 102 and a signal from within logic circuit 103 and generate signals at output terminals (OUT1 to OUTn), respectively.
During burn-in operation, vector generator circuit 112 and refresh counter and control circuit 106 generates addresses, instructions, and data for operating DRAM 102 based upon vector generation control signal MBICMD, write data initial values (DIN0 to DINn), data inversion control signal DININV, read signal LDRD, and write signal LDWT. DRAM 102 is operated in accordance with those addresses, instructions, and data during the burn-in operation.
Along with a test mode signal TM, logic circuit 103 is also operated in response to vector generation control signal MBICMD, write data initial values (DIN0 to DINn), data inversion control signal DININV, read signal LDRD, and write signal LDWT during burn-in operation.
In this way, DRAM 102 and logic circuit 103 are simultaneously operated during burn-in operation and burn-in test time is shortened.
As described above, in a burn-in operation of conventional semiconductor integrated circuit 101, extra input signals may be needed. However, the greater the number of input signals, the more input/output pins are required in a semiconductor integrated circuit. A burn-in apparatus or tester can be limited by the number of input/output pins. This can be due to limited bandwidth, as just one example. During a burn-in test, many devices may be tested in parallel. By having a large number of functioning input/output pins per device, the bandwidth of the tester can be limited because it may not be desirable to test too many devices in parallel being controlled by the same signal lines due to increased loads and tester limitations.
Thus, it is desirable that the number of input signals needed in a burn-in test be reduced. This can allow costs to be decreased by allowing a larger number of semiconductor integrated circuits to be tested simultaneously.
Also, when a large number of input signals are used, such as in a conventional semiconductor integrated circuit, a large number of test patterns of input signals is increased and complexity is increased. This can increase test time and cost. It is preferable to reduce the number of patterns in order to decrease cost.
In view of the above discussion, it would be desirable to provide semiconductor device which may be capable of executing a burn-in operation in a memory and a logic circuit simultaneously without increasing the number of input signals inputed from the outside.
According to the present embodiments, a semiconductor integrated circuit having a normal operation mode and a burn-in mode is provided. The semiconductor integrated circuit may include a memory and a logic circuit. The memory may operate in response to input signals when in the burn-in mode while the logic circuit may operate in response to control signals generated in response to one of the input signals having a predetermined value when the semiconductor integrated circuit operates in the burn-in mode. The memory may operate in response to memory control signals generated by the logic circuit when the semiconductor integrated circuit operates in the normal operation mode. The logic circuit may generate the memory control signal in response to values provided by the input signals. In this way, the logic circuit and memory may be tested in the burn-in mode without providing additional inputs.
According to one aspect of the embodiments, a semiconductor integrated circuit may have a burn-in mode and an ordinary operation mode. The semiconductor integrated circuit may include a memory operable in response to a plurality of input signals when the semiconductor integrated circuit is in the burn-in mode. A logic generator circuit may provide control signals in response to at least one of the plurality of input signals when the semiconductor integrated circuit is in the burn-in mode. A logic circuit may operate in response to the control signals.
According to another aspect of the embodiments, when the semiconductor integrated circuit is in the ordinary operation mode, the logic generator circuit may provide control signals having logic values dependent on the logic value of the plurality of input signals. The logic circuit may provide at least one memory control signal in response to the control signals. The memory may be operated in response to the at least one memory control signal.
According to another aspect of the embodiments, the semiconductor integrated circuit may include a pattern detection circuit coupled to receive the plurality of input signals. The pattern generator circuit may generate a logic circuit enable signal having a logic circuit enable state and a logic circuit disable state. During the normal operation mode, the logic circuit enable signal may have the logic circuit enable state in response to the pattern detection circuit detecting a predetermined pattern included in the plurality of input signals.
According to another aspect of the embodiments, the logic circuit enable signal may have the logic circuit enable state when the semiconductor integrated circuit is in the burn-in mode.
According to another aspect of the embodiments, the plurality of input signals may be digital signals, each having a logic value. When the semiconductor integrated circuit is in the burn-in mode, the logic generator circuit may periodically detect the logic value of at least one of the plurality of input signals and may change the logic value of the control signals if the logic value of at least one of the plurality of input signals is a predetermined logic value.
According to another aspect of the embodiments, the logic circuit may include a pattern generator, that may change the logic value of the control signals if the logic value of a predetermined on of the plurality of input signals has the predetermined logic value.
According to another aspect of the embodiments, a method of operating a semiconductor integrated circuit capable of operating in a burn-in mode and an ordinary operation mode may include the steps of receiving an input signal, operating a memory in response to the input signal during the burn-in mode, generating a logic circuit operation signal based on the input signal during the burn-in mode, and operating a logic circuit in response to the logic circuit operation signal.
According to another aspect of the embodiments, the method of operating the semiconductor integrated circuit may include the steps of generating a logic circuit control signal having a value substantially the same as the value of the input signal during the ordinary operation mode, operating the logic circuit in response to the logic circuit control signal and outputting a memory control signal, and operating the memory in response to the memory control signal.
According to another aspect of the embodiments, the method of operating the semiconductor integrated circuit may include the steps of generating a logic circuit allowance signal for instructing whether or not operation of the logic circuit is allowed.
According to another aspect of the embodiments, the step of generating the logic circuit allowance signal may include the steps of generating the logic circuit allowance signal such that operation of the logic circuit is allowed during the burn-in mode, detecting whether or not a predetermined pattern is included in the input signal during the ordinary operation mode, generating the logic circuit allowance signal such that operation of the logic circuit is allowed when the predetermined pattern is included in the input signal during the ordinary operation mode, and generating the logic circuit allowance signal such that operation of the logic circuit is prohibited when the determined pattern is not included in the input signal during the ordinary operation mode.
According to another aspect of the embodiments, a semiconductor integrated circuit may include a stress test mode and an ordinary operation mode. The semiconductor integrated circuit may include a memory circuit operable in response to a group of inputs signals when the semiconductor integrated circuit is in the stress test mode. A logic generator circuit may provide control signals in response to at least one of the inputs signals from the group of inputs signals when the semiconductor integrated circuit is in the stress test mode. A logic circuit may operate in response to the control signals.
According to another aspect of the embodiments, the logic generator circuit may include a trigger bit detection circuit providing a trigger signal in response to at least one of the input signals from the group of input signals. The logic generator circuit may modify a logic value of at least one of the control signals in response to the trigger signal when the semiconductor integrated circuit is in the stress test mode.
According to another aspect of the embodiments, the logic generator circuit may include a pattern generator circuit generating the control signals in response to the trigger signal when the semiconductor integrated circuit is in the stress test mode.
According to another aspect of the embodiments, the pattern generator circuit may include a status pointer circuit that increments a stored status value in response to the trigger signal when the semiconductor integrated circuit is in the stress test mode.
According to another aspect of the embodiments, the semiconductor integrated circuit may include a pattern detection circuit that generates a pattern hit signal having a pattern detected state in response to the group of input signals having a predetermined pattern when the semiconductor integrated circuit is in the ordinary operation mode and when the pattern hit signal has the pattern detected state the logic circuit is allowed to operate in response to the control signals.
According to another aspect of the embodiments, the pattern signal may have the pattern detected state regardless as to whether the group of input signals has the predetermined pattern when the semiconductor integrated circuit is in the stress test mode.
According to another aspect of the embodiments, the group of input signals may provide data in a serial fashion. The logic circuit may include a serial to parallel conversion circuit that converts the group of input signals into parallel signals to provide the control signals when the semiconductor integrated circuit is in the ordinary operation mode.
According to another aspect of the embodiments, the logic circuit may provide memory control signal when the semiconductor integrated circuit is in the ordinary operation mode.
According to another aspect of the embodiments, the semiconductor integrated circuit may include a first test mode. The logic circuit may be disabled in the first test mode. The memory circuit may be operable in response to the group of input signals when the semiconductor integrated circuit is in the first test mode.
According to another aspect of the embodiments, the stress test mode may be a burn-in test mode.